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-- Company: BASH Robotics
-- Engineer: Will Rozzo
-- 
-- Create Date:    13:39:35 07/18/2009 
-- Design Name: 
-- Module Name:    DeviceMemory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- 256x32 256 addresses each 32 bits long
entity DeviceMemory is
    Port ( 	currState : in STD_LOGIC_VECTOR( 1 downto 0 ); -- I think we are cool with 4 states for now, can add more later
				clk : in STD_LOGIC;
				rst : in STD_LOGIC;
				inPkt : in  STD_LOGIC_VECTOR(31 downto 0 );
				address : in STD_LOGIC_VECTOR( 7 downto 0 ); -- I have no idea how many addresses we will need this is 256
				outPkt : out STD_LOGIC_VECTOR(31 downto 0));
end DeviceMemory;

architecture Behavioral of DeviceMemory is

type DEV_MEM is array(255 downto 0) of std_logic_vector(31 downto 0);  -- Array of packets
signal mem_data : DEV_MEM;

begin 

--STATES
-- 00: IDLE
-- 01: READ
-- 10: WRITE
-- 11: ??

	memproc : process(clk,address) is
	begin
		if( rising_edge(clk) )then
			if( currState = "10" )  then-- WRITE
				mem_data(conv_integer(address)) <= inPkt;  
			elsif( currState = "01" ) then -- READ
				outPkt <= mem_data(conv_integer(address));
			end if;
		end if;
	end process memproc;
	
	ResetMem : process( clk, rst ) is
	begin
		if( rising_edge(clk) and rst = '1' ) then
			for i in 0 to 256 loop
				mem_data(i) <= "00000000000000000000000000000000";
			end loop;
		end if;
	end process ResetMem;


end Behavioral;

